Hardware reduction for Moore FSM implemented with CPLD, 2009, Oleksandr Barkalov , Larysa Titarenko , Sławomir Chmielewski , Electronics and Telecommunications Quarterly, Vol. 55, no 2, 317--333, bibliogr. rys. tab. wykr. summ.
Słowa kluczowe: CPLD, Moore finite-state-machine, PAL, graph-scheme of algorithm, macrocell, pseudoequivalent states, synthesis
Kod: CZR-WYKAZ BibTeX (pkt. 6)

Petri nets mapping into reconfigurable logic controllers, 2009, Marian Adamski , Marek Węgrzyn , Electronics and Telecommunications Quarterly, Vol. 55, no 2, 157--182, bibliogr. rys. tab. summ.
Słowa kluczowe: FPGA, HDL, PNSF2, Petri net, VHDL, logic controller, modeling, place encoding, programmable logic, synthesis, verilog
Kod: CZR-WYKAZ BibTeX (pkt. 6)

Optimization of compositional microprogram control unit by modification of microinstruction format, 2009, Larysa Titarenko , Jacek Bieganowski , Electronics and Telecommunications Quarterly, Vol. 55, no 2, 201--214, bibliogr. rys. tab. summ.
Słowa kluczowe: CPLD, compositional microprogram control unit, flow-chart of algorithm, microinstruction
Kod: CZR-WYKAZ BibTeX (pkt. 6)

Structural decomposition of finite state machines, 2009, Arkadiusz Bukowiec , Oleksandr Barkalov , Electronics and Telecommunications Quarterly, Vol. 55, no 2, 243--267, bibliogr. rys. tab. summ.
Słowa kluczowe: FPGA, FSM, control unit, decomposition, synthesis
Kod: CZR-WYKAZ BibTeX (pkt. 6)

Structural decomposition of microprogrammed controllers, 2009, Remigiusz Wiśniewski , Oleksandr Barkalov , Electronics and Telecommunications Quarterly, Vol. 55, no 2, 215--241, bibliogr. rys. summ.
Słowa kluczowe: compositional microprogram control units, control units, field programmable gate arrays, microprogramed controllers, programmable devices
Kod: CZR-WYKAZ BibTeX (pkt. 6)