PERS - System Informacji o Pracownikach

SKEP - Wyniki wyszukiwania wśród publikacji


Szukanie:
w opisie bibliograficznym
Wprowadzona fraza:
{Journal of Circuits Systems and Computers}
Opublikowano w latach:
1960 - 2024
Znaleziono:
6 (spośród około 72877)
Z frazy usunięto:
,

1.
Mixed Encoding of Collections of Output Variables for LUT-Based Mealy FSMs, 2018, Oleksandr Barkalov , Larysa Titarenko , Sławomir Chmielewski , Journal of Circuits, Systems and Computers, Vol. 28, no. 8, 1--21, ISSN: 0218-1266, bibliogr. rys. tab. summ.
Słowa kluczowe: FPGA, LUT, mealy FSM, output variables, partition, synthesis
Kod: CZR-JCR BibTeX (pkt. 15) DOI: 10.1142/S0218126619501317
Cytowania wg WOS: 5 [02-05-2024], JIF: 0.939
[AWCZ-23152] [data modyf. 22-06-2022 13:52]

2.
Design of multi-context reconfigurable logic controllers implemented in FPGA devices oriented for further partial reconfiguration, 2018, Remigiusz Wiśniewski , Iwona Grobelna , Journal of Circuits, Systems and Computers, Vol. 27, iss. 6, 1--25, ISSN: 0218-1266, bibliogr. summ.
Słowa kluczowe: FPGA, Petri net, decomposition, formal verification, model checking, partial reconfiguration, reconfigurable logic controllers
Kod: CZR-JCR BibTeX (pkt. 15) DOI: 10.1142/S021812661850086X
Cytowania wg WOS: 10 [02-05-2024], JIF: 0.939
[AWCZ-21635] [data modyf. 22-06-2022 13:52]

3.
Design of EMB-Based Moore FSMs, 2017, Małgorzata Mazurkiewicz , Larysa Titarenko , Oleksandr Barkalov , Journal of Circuits, Systems and Computers, Vol. 26, no. 7, 1--23, ISSN: 0218-1266, bibliogr. rys. tab. summ.
Słowa kluczowe: Finite-state machine, design, field-programmable gate array, logic circuit
Kod: CZR-JCR BibTeX (pkt. 15) DOI: 10.1142/S0218126617501250
Cytowania wg WOS: 0 [02-05-2024], JIF: 0.595
[AWCZ-21182] [data modyf. 22-06-2022 13:51]

4.
Hardware reduction in CPLD-based Moore FSM, 2014, Oleksandr Barkalov , Larysa Titarenko , Sławomir Chmielewski , Journal of Circuits, Systems and Computers, Vol. 23, no. 6, 1--21, ISSN: 0218-1266, bibliogr. rys. tab. summ.
Słowa kluczowe: CPLD, Moore FSM, logic synthesis, pseudoequivalent states, state assignment
Kod: CZR-JCR BibTeX (pkt. 15)
JIF: 0.250
[AWCZ-18234] [data modyf. 20-04-2021 14:09]

5.
Hardware reduction in FPGA-based moore FSM, 2013, Oleksandr Barkalov , Larysa Titarenko , R. V. Malheva , K. A. Soldatov , Journal of Circuits, Systems and Computers, Vol. 22, no. 3, 1--20, ISSN: 0218-1266, bibliogr. rys. tab. summ.
Słowa kluczowe: EMB, FPGA, GSA, LUT, moore FSM, pseudoequivalent states
Kod: CZR-JCR BibTeX (pkt. 15) DOI: 10.1142/S0218126613500060
Cytowania wg WOS: 7 [02-05-2024], JIF: 0.330
[AWCZ-17298] [data modyf. 06-04-2021 13:59]

6.
LMI-based analysis for continuous-discrete linear shift-invariant nD systems, 2005, Jacek Bochniak , Krzysztof Gałkowski , Journal of Circuits, Systems and Computers, Vol. 14, no 2, 307--332, ISSN: 0218-1266, bibliogr. summ.
Słowa kluczowe: Linear Matrix Inequality (LMI), continuous-discrete (hybrid) systems, multidimensional (nD) systems, robust stability, robust stabilization, stability, stability margins, stabilization, stabilization to the prescribed stability margins, uncertainty
Kod: CZR-JCR BibTeX (pkt. [?])
[AWCZ-10331] [data modyf. 20-04-2021 14:09]