Mixed Encoding of Collections of Output Variables for LUT-Based Mealy FSMs,
2018,
Oleksandr Barkalov ,
Larysa Titarenko ,
Sławomir Chmielewski ,
Journal of Circuits, Systems and Computers, Vol. 28, no. 8, 1--21, ISSN: 0218-1266,
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Słowa kluczowe: FPGA, LUT, mealy FSM, output variables, partition, synthesis
Kod: CZR-JCR
BibTeX
(pkt. 15)
DOI: 10.1142/S0218126619501317